Lead Functional Product Engineer, Power Analysis

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 114,800 - 213,200 annuallyFunction: Energy & Utilities OperationsExperience: 3+ yearsEducation: bachelorsSkills: ["Debugging","Technical support","Documentation","Collaboration","Problem-solving"]

Join the Power Analysis team to develop, debug, and deploy Signoff power analysis flows for customer environments. You’ll work with R&D to integrate flows across synthesis and PnR, reproduce and resolve customer issues, and provide hands-on technical support at customer sites. The role also includes collaborating with customers to optimize power results, contributing automation via scripting, and documenting best practices and flow guidelines.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Lead Functional Product Engineer, Power Analysis

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Join the Power Analysis team to develop, debug, and deploy Signoff power analysis flows for customer environments. You’ll work with R&D to integrate flows across synthesis and PnR, reproduce and resolve customer issues, and provide hands-on technical support at customer sites. The role also includes collaborating with customers to optimize power results, contributing automation via scripting, and documenting best practices and flow guidelines.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Energy & Utilities Operations
Seniority: Mid level

Key Responsibilities

  • •Develop and maintain Signoff power analysis flows, including integration with synthesis and PnR stages.
  • •Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows.
  • •Deploy and validate power analysis tools at customer sites and provide hands-on technical support.
  • •Collaborate with customers to optimize power results and improve flow efficiency.
  • •Contribute to flow automation and scripting for repeatable deployments, and document findings and best practices.

Pay and Benefits

Salary: USD 114,800 - 213,200 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kHealth InsuranceDentalVisionEquity

Key Requirements

  • •Hands-on experience with Signoff power analysis (static and dynamic power).
  • •Working knowledge of UPF, including power domains, isolation, level shifting, and retention.
  • •Proficiency in Verilog/SystemVerilog for design analysis and testcase creation.
  • •Knowledge of power optimization techniques in synthesis (e.g., clock gating, operand isolation, multi-Vt cell selection) and digital timing/power trade-offs.
  • •Scripting skills in Tcl, Python, or Shell and 3+ years of industry work experience.
Experience:3+ years
Education:Bachelor's in Electronics / VLSI / Computer Engineering
Skills:DebuggingTechnical supportDocumentationCollaborationProblem-solving
Tech Stack:Signoff power analysisSynthesisPnRUPFVerilogSystemVerilogTclPythonShellLiberty (.lib)SPEFJoulesVoltusPTPX

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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