Sr Principal Design Engineer

Cadence Design Systems
Seoul
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsSkills: ["Independent work","Teamwork","Self-motivation","Communication"]

Own ASIC physical design implementation for Cadence Korea, delivering floorplanning through place-and-route, clock tree synthesis, timing closure, and power/signal integrity signoff. Perform physical verification (DRC/LVS/Antenna), EM/IR signoff, and DFM closure while working on low-power and high-speed designs at advanced technology nodes. Participate in or lead next-generation physical design methodology and flow development, partnering with the RTL team to support successful tapeouts.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
10 hours ago

Sr Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Own ASIC physical design implementation for Cadence Korea, delivering floorplanning through place-and-route, clock tree synthesis, timing closure, and power/signal integrity signoff. Perform physical verification (DRC/LVS/Antenna), EM/IR signoff, and DFM closure while working on low-power and high-speed designs at advanced technology nodes. Participate in or lead next-generation physical design methodology and flow development, partnering with the RTL team to support successful tapeouts.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform physical design implementation including floor planning, power grid design, place and route, and clock tree synthesis.
  • •Drive timing closure and power/signal integrity signoff.
  • •Conduct physical verification (DRC/LVS/Antenna), EM/IR signoff, and DFM closure.
  • •Work on challenging low power and high speed designs at latest technology nodes.
  • •Participate in or lead next-generation physical design methodology and flow development, collaborating with RTL to support tapeouts.

Key Requirements

  • •15+ years of experience with ASIC design flow, including hierarchical physical design strategies and deep sub-micron technology understanding.
  • •Solid knowledge of Low Power Design, DFT, and static timing analysis/closure.
  • •Hands-on capability across the physical design flow, including data skew balancing and duty cycle adjustment.
  • •Experience with EM/IR-drop/crosstalk analysis, formal verification, physical verification, and DFM and P&R.
  • •Strong ability to take responsibility for technical tasks independently, and good English communication skills.
Experience:15+ yearsASIC designPhysical designLow powerHigh speed
Skills:Independent workTeamworkSelf-motivationCommunication
Languages:English
Tech Stack:ASICPhysical designFloor planningPower grid designPlace and routeClock tree synthesisTiming closurePower/signal integrity signoffPhysical verificationDRCLVSAntennaEM/IR signoffDFM closureLow power designDFTStatic timing analysisData skew balancingDuty cycle adjustmentEM/IR-drop

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor