RTL Design Engineer

AMD
Markham
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","TCL","Python","Perl","Ruby","Makefile","AXI","AMBA","DFT","Linting","Synthesis","Simulation"]

Join AMD as an RTL Design Engineer in the SECIP team, designing and verifying block-level RTL IP and MP subsystems for SoCs across client, server, graphics, and gaming products. You’ll own micro-architecture, collaborate on verification plans, debug RTL with C-DPI and testbenches, resolve regressions and timing/DFT issues, and mentor teammates while shaping high-performance hardware accelerators and cryptography-related functionality.

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FursaFursa
AMD
AMD
2 months ago

RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Join AMD as an RTL Design Engineer in the SECIP team, designing and verifying block-level RTL IP and MP subsystems for SoCs across client, server, graphics, and gaming products. You’ll own micro-architecture, collaborate on verification plans, debug RTL with C-DPI and testbenches, resolve regressions and timing/DFT issues, and mentor teammates while shaping high-performance hardware accelerators and cryptography-related functionality.
Location: Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop and maintain block-level RTL IP and MP subsystems’ feature specs, micro-architecture, synthesizable RTL design methodology and infrastructure
  • •Develop and debug RTL designs using C-DPI directed test methodology and verification testbenches to achieve feature closure
  • •Triage regressions, debug simulations, analyze coverage, and resolve issues with design/verification teams to achieve design feature and rule closures (linting, timing, DFT, DFP)
  • •Participate in verification testbench and test plan specification, influence testbench architecture development and improve feature/coverage plans
  • •Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams

Key Requirements

  • •Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent; Master’s Degree preferred
  • •Proficient in Verilog and SystemVerilog; scripting experience in Tcl, Ruby, Perl, Python and Makefile
  • •Excellent knowledge of RTL design and verification methodologies and C-DPI test design
  • •Strong understanding of standard bus/interface protocols (AXI, AHB, AMBA)
  • •Experience with ASIC design tools: synthesis, linting, simulation, debugging, power-aware simulation
Experience:SemiconductorEmbeddedSoC
Education:Bachelor's
Skills:VerilogSystemVerilogTCLPythonPerlRubyMakefileAXIAMBADFTLintingSynthesisSimulation
Languages:English
Tech Stack:VerilogSystemVerilogTCLRubyPerlPythonMakefileAXIAHBAMBAASIC toolsSynthesisLintingSimulationC-DPI

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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