Principal Physical Design Engineer (Chiplet Design)

AMD
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: bachelorsSkills: ["Communication","Presentation","Collaboration","Mentoring","Interpersonal skills"]

Own end-to-end physical design for a complete chiplet on advanced technology nodes (preferably TSMC 2nm/3nm). Drive full chip floorplan and define timing targets across PVTs, pushing full chip PnR and tile PnR closure while monitoring signoff functions such as physical verification and IREM. Balance power, performance, and area, coordinate closely with architects, IP, CAD/methodology, and package teams, and sign off the chiplet for tapeout.

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FursaFursa
AMD
AMD
4 months ago

Principal Physical Design Engineer (Chiplet Design)

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Last checked: 1 hour agoStatus: Live

Job Summary

Own end-to-end physical design for a complete chiplet on advanced technology nodes (preferably TSMC 2nm/3nm). Drive full chip floorplan and define timing targets across PVTs, pushing full chip PnR and tile PnR closure while monitoring signoff functions such as physical verification and IREM. Balance power, performance, and area, coordinate closely with architects, IP, CAD/methodology, and package teams, and sign off the chiplet for tapeout.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own the physical design for one complete chiplet on advanced technology nodes, preferably TSMC 2nm or 3nm.
  • •Coordinate with external stakeholders (architects, IP teams, CAD/methodology) and internal PD stakeholders on physical design topics.
  • •Drive best PPA attainments and optimize latency on datapaths while working with package teams on power delivery and dependencies.
  • •Signoff the chiplet for tapeout from a physical design perspective.
  • •Collaborate across teams in different geographies and elevate team knowledge through mentoring and guidance.

Key Requirements

  • •15+ years of experience in physical design handling full chip activities and signoff.
  • •Experience driving full chip floorplan based on architecture and defining timing targets across PVTs.
  • •Proven ability to drive full chip PnR and tile PnR closure and monitor signoff functions such as physical verification and IREM.
  • •Strong communication, management, and presentation skills, including technical publications and executive briefings.
  • •Bachelor’s or Master’s degree in a related discipline preferred.
Experience:15+ yearsSemiconductorPhysical designChipletVLSI
Education:Bachelor's
Skills:CommunicationPresentationCollaborationMentoringInterpersonal skills
Tech Stack:Physical designChipletFloorplanTiming targetsPVTPnRTile PnRPPATSMC 2nmTSMC 3nmPhysical verificationIREMTapeoutPower deliveryData paths

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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