RTL Design Engineer
Hyderabad
Workplace: OnsiteFull timeINR 3,383,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Verilog","VCS","Perl","Shell","PCIe","NVMe","Ethernet","TCP/IP","RDMA"]ASIC RTL Design Engineer leading IP development for programmable logic silicon, across architecture to productization. Role involves architecture definition, RTL design and integration, and crossing cross-functional teams for testing, compliance, and verification with strong emphasis on Verilog, IP workflows, and silicon tapeouts.
Loading
Loading job details...
Preparing the role view and application actions.

