Physical Design Engineer

Own the RTL-to-GDSII physical design flow for complex mixed-signal SoC/ASIC blocks. Execute synthesis, floorplanning, placement, clock tree synthesis, routing, and timing closure across multiple corners and modes using static timing analysis. Optimize area, power, and performance, update constraints, and run physical signoff checks such as DRC, LVS, IR-drop, and EM. Collaborate with RTL, verification, and architecture teams and support EDA flow automation via scripting.