Physical Design Engineer

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2-5 yearsEducation: mastersSkills: ["Communication","Collaboration","Problem-solving","Debugging","Analytical"]

Own the RTL-to-GDSII physical design flow for complex mixed-signal SoC/ASIC blocks. Execute synthesis, floorplanning, placement, clock tree synthesis, routing, and timing closure across multiple corners and modes using static timing analysis. Optimize area, power, and performance, update constraints, and run physical signoff checks such as DRC, LVS, IR-drop, and EM. Collaborate with RTL, verification, and architecture teams and support EDA flow automation via scripting.

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FursaFursa
Texas Instruments
Texas Instruments
3 months ago

Physical Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Own the RTL-to-GDSII physical design flow for complex mixed-signal SoC/ASIC blocks. Execute synthesis, floorplanning, placement, clock tree synthesis, routing, and timing closure across multiple corners and modes using static timing analysis. Optimize area, power, and performance, update constraints, and run physical signoff checks such as DRC, LVS, IR-drop, and EM. Collaborate with RTL, verification, and architecture teams and support EDA flow automation via scripting.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Execute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.
  • •Perform logic synthesis, floorplanning, placement, CTS, and routing.
  • •Develop and maintain design constraints.
  • •Drive timing closure across multiple corners and modes using static timing analysis.
  • •Conduct physical verification and signoff checks (DRC, LVS, antenna checks, IR-drop, EM analysis), and support tape-out activities.

Key Requirements

  • •M.E./M.Tech or B.E./B.Tech in Electronics, Electrical, VLSI, or a related field.
  • •2-5 years of hands-on physical design experience for ASIC/SoC.
  • •Strong knowledge of CMOS, VLSI design fundamentals, and digital circuit concepts.
  • •Proficiency with EDA tools such as Cadence (Innovus, Tempus, voltus) or equivalent.
  • •Experience with physical signoff checks including DRC, LVS, IR drop, EM, and noise analysis.
Experience:2-5 years
Education:Master's
Skills:CommunicationCollaborationProblem-solvingDebuggingAnalytical
Tech Stack:RTLGDSIICMOSVLSICadenceInnovusTempusVoltusStatic timing analysisSTAFloorplanningPlacementClock tree synthesisCTSRoutingDRCLVSIR-dropEM analysisNoise analysis

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn