Design for Test Lead

Neurophos
Austin, Sunnyvale
Workplace: OnsiteFull timeUSD 225,000 - 300,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8-15 yearsSkills: ["Ownership","Collaboration","Test strategy","Cross-functional partnering","Reasoning"]

Own design-for-test (DFT) architecture for multiple ASIC devices, setting the chip-level DFT strategy and driving scan (stuck-at/at-speed), MBIST, and boundary scan/JTAG test control. Define on-die memory test and system-level wafer/package DFT plans across development phases, integrate test modes (including HAST), and deploy production test plans to OSAT. Partner with RTL, physical design, and analog teams to build testability early and ensure near-100% coverage with coverage signoff and post-silicon handoff.

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FursaFursa
Neurophos
Neurophos
19 hours ago

Design for Test Lead

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 minutes agoStatus: Live

Job Summary

Own design-for-test (DFT) architecture for multiple ASIC devices, setting the chip-level DFT strategy and driving scan (stuck-at/at-speed), MBIST, and boundary scan/JTAG test control. Define on-die memory test and system-level wafer/package DFT plans across development phases, integrate test modes (including HAST), and deploy production test plans to OSAT. Partner with RTL, physical design, and analog teams to build testability early and ensure near-100% coverage with coverage signoff and post-silicon handoff.
Location: Austin, Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Own DFT architecture and test control design for multiple ASIC devices using ATPG scan, MBIST, and boundary scan/JTAG, including MCM and external HBM module DFT capabilities.
  • •Architect on-die memory test, including controller specification, pattern selection, RAM grouping, and system test time and power analysis.
  • •Ensure all test modes are fully implemented in coordination with operations and PE teams, including HAST and other qualification functions.
  • •Create system-level wafer and package-level DFT plans across all product development phases and deploy an integrated DFT development flow with key metrics for rapid iteration toward near-100% coverage.
  • •Specify and deliver production-level test plans to OSAT, including coverage assessment/signoff and handoff into the post-silicon test program, with functional vectors and analog test requirements.

Pay and Benefits

Salary: USD 225,000 - 300,000 annually
Perks:Health InsuranceHsa ContributionsPaid Leave401k MatchingEquityDentalVisionLife InsuranceAccident Insurance

Key Requirements

  • •8 to 15 years in DFT with hands-on ownership of scan, ATPG, and MBIST.
  • •Architect-level experience on a large digital ASIC, including full-chip DFT strategy and coverage signoff.
  • •Experience developing and specifying functional test vectors to augment structural coverage.
  • •Track record through tapeout on a complex compute ASIC.
  • •Experience building testability into RTL and partnering with RTL and physical design teams early.
Experience:8-15 yearsDigital ASICCompute ASICSemiconductorAI hardware
Skills:OwnershipCollaborationTest strategyCross-functional partneringReasoning
Tech Stack:DFTATPGScanStuck-atAt-speedMBISTBoundary scanJTAGMCMHBMOn-die memory testRAM groupingHASTRTLPhysical designFunctional test vectorsCadenceOSATPost-silicon test

Company Brief

Neurophos
Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Growth Stage Startup
Funding: Series A
Headquarters: Austin, United States
Founded: 2020
WebsiteLinkedIn