Photonic Layout Engineer - New Grad

Ciena
Ottawa
Workplace: OnsiteFull timeUSD 61,800 - 98,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 3+ yearsEducation: bachelorsSkills: ["Organizational skills","Attention to detail","Communication","Collaboration"]

Collaborate with the Photonic Integrated Circuit (PIC) Design team to create photomask layouts for photonic chips. Partner closely with device design and semiconductor fabrication teams to ensure layouts meet process constraints, and perform quality control through mask review and design rule checking. Build and improve automated layout tools using scripting, and communicate effectively with multidisciplinary internal teams and external foundry partners to help enable advanced photonic components for future optical networks.

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FursaFursa
Ciena
Ciena
1 month ago

Photonic Layout Engineer - New Grad

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Source: Company careers pageValidated by: Fursa AI
Last checked: 29 days agoStatus: Live

Job Summary

Collaborate with the Photonic Integrated Circuit (PIC) Design team to create photomask layouts for photonic chips. Partner closely with device design and semiconductor fabrication teams to ensure layouts meet process constraints, and perform quality control through mask review and design rule checking. Build and improve automated layout tools using scripting, and communicate effectively with multidisciplinary internal teams and external foundry partners to help enable advanced photonic components for future optical networks.
Location: Ottawa
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Graduate level

Key Responsibilities

  • •Generate and maintain photomask layout designs for photonic chips.
  • •Perform quality control, including mask review, to ensure manufacturability.
  • •Develop automated layout tools, including design rule checks and scripting.
  • •Serve as the link between device design and semiconductor fabrication process constraints.
  • •Collaborate with multidisciplinary internal teams and external foundry partners through clear communication.

Pay and Benefits

Salary: USD 61,800 - 98,800 annually
Perks:Health InsuranceDentalVision401kEsppEapPaid Leave

Key Requirements

  • •BS degree or higher in a related engineering or science field (e.g., electrical engineering or material sciences).
  • •3+ years of experience using a layout editor such as L-Edit, DW2000, or Cadence for semiconductor device layout.
  • •Experience scripting masks and proficiency in at least one programming language such as C/C++ or Python.
  • •Familiarity with semiconductor wafer fabrication methods (e.g., III-V, Si).
  • •Good understanding of semiconductor device physics and principles, including design rule checking and layout verification tools.
Experience:3+ years
Education:Bachelor's
Skills:Organizational skillsAttention to detailCommunicationCollaboration
Tech Stack:L-EditDW2000CadenceCC++Python

Company Brief

Ciena
Provides networking systems, software, and services that enable service providers, cloud operators, and enterprises to deliver high-capacity connectivity and adaptive network solutions worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Hanover, United States
Founded: 1992
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Glassdoor: 3.8
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