DFT Design Engineer

Intel
India
Workplace: HybridContractFunction: Design (Product/UX/UI/Visual)Experience: 2+ yearsEducation: bachelorsSkills: []

Design and implement DFT solutions for silicon validation, leveraging Spyglass DFT and SSN topology to build and debug JTAG, Memory BIST, and Memory Repair circuitry. Verify designs using gate-level simulation with timing annotations, improve ATPG coverage, and resolve simulation failures and DRC issues. Analyze DFT mode timing constraints and partner with post-silicon/manufacturing teams to debug and resolve ATE-related problems.

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FursaFursa
Intel
Intel
4 days ago

DFT Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Design and implement DFT solutions for silicon validation, leveraging Spyglass DFT and SSN topology to build and debug JTAG, Memory BIST, and Memory Repair circuitry. Verify designs using gate-level simulation with timing annotations, improve ATPG coverage, and resolve simulation failures and DRC issues. Analyze DFT mode timing constraints and partner with post-silicon/manufacturing teams to debug and resolve ATE-related problems.
Location: India
Workplace: Hybrid
Employment Type: Contract
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Implement DFT circuitry including JTAG, Memory BIST, and Memory Repair (BIRA/BISR) using industry-standard tools.
  • •Perform DFT verification using gate-level simulations with timing annotations.
  • •Investigate and resolve DFT problems such as simulation failures, ATPG coverage improvements, and DRC debug.
  • •Analyze timing constraints and conduct DFT mode timing analysis.
  • •Collaborate with post-silicon/manufacturing teams on ATE to debug and resolve issues.

Key Requirements

  • •B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 2+ years of DFT experience.
  • •Strong experience with Spyglass DFT, Scan Architecture (SSN Topology), ATPG, and fault models.
  • •Hands-on ability to implement JTAG, Memory BIST, and Memory Repair (BIRA/BISR) circuitry using standard tools.
  • •Experience with DFT verification using gate-level simulations with timing annotations and solving DFT issues (simulation failures, ATPG coverage improvements, DRC debug).
  • •Proficiency in timing constraints/mode timing analysis, plus RTL coding and shell scripting, and experience working with post-silicon/manufacturing teams on ATE debugging.
Experience:2+ years
Education:Bachelor's in Electrical/Electronics/Communication Engineering
Tech Stack:Spyglass DFTScan ArchitectureSSN TopologyATPGFault modelsJTAGMemory BISTMemory RepairBIRABISRDFT verificationGate Level SimulationsTiming annotationsDRC debugTiming constraintsRTL codingShell scriptingPost-SiliconManufacturing teamsATE

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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Glassdoor: 3.8
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