CPU Floorplan Lead

Intel
Bengaluru
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 10+ yearsEducation: bachelorsSkills: ["Collaboration","Problem-solving","Capacity planning","Design evaluation","Physical convergence"]

Own the physical dimensions and floorplanning of CPU IP, optimizing die size, die-per-reticle/wafer yield, and technology choices. Drive integration of dies in packages, create physical databases/specifications, and collaborate with architecture, clock, logic, power-delivery, DFT, and package teams to deliver floorplans for APR and tapeout readiness. Evaluate floorplanning tools/methods, set planning boundaries and pin densities, and resolve issues across partition/cluster and full-chip integration.

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Intel
Intel
3 days ago

CPU Floorplan Lead

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Last checked: 13 hours agoStatus: Live

Job Summary

Own the physical dimensions and floorplanning of CPU IP, optimizing die size, die-per-reticle/wafer yield, and technology choices. Drive integration of dies in packages, create physical databases/specifications, and collaborate with architecture, clock, logic, power-delivery, DFT, and package teams to deliver floorplans for APR and tapeout readiness. Evaluate floorplanning tools/methods, set planning boundaries and pin densities, and resolve issues across partition/cluster and full-chip integration.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Lead floorplan and pin placement activities across the design cycle.
  • •Partner with architecture, DFT, and package teams to achieve optimal chip planning and floorplans early.
  • •Create specifications and collaterals for IP blocks to execute floorplanning and APR at subsequent hierarchies.
  • •Collaborate with physical design cluster leads to address partition/cluster and full-chip design challenges and issues.
  • •Set planning boundaries, pin densities, and die size estimation to support timing closure and routability for tapeout readiness.

Key Requirements

  • •B.Tech. or M.Tech. in Electrical-Electronics Engineering with 10+ years of experience.
  • •10+ years’ experience across ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
  • •Minimum 4 years in floor planning, with expert use of floorplanning tools such as ICC2 DP or Cadence Encounter.
  • •Experience with SoC issues including multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and advanced package technologies.
  • •Knowledge of design for yield and manufacturability and the ability to handle hierarchical, top-down budgeting, timing, and physical convergence.
Experience:10+ yearsASICSoC
Education:Bachelor's in Electrical-Electronics Engineering
Skills:CollaborationProblem-solvingCapacity planningDesign evaluationPhysical convergence
Tech Stack:ASICSoCFloorplanningICC2 DPCadence EncounterAPRPhysical design verificationP and R flowsClock distributionPower deliveryESD strategiesMixed-signal

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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Glassdoor: 3.8
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