Senior Engineer IP Verification - Digital Design Verification
Hyderabad, Telangana, India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4-6 yearsEducation: bachelorsSkills: ["Communication","Debugging","Teamwork","Stakeholder communication","Proactive learning","Risk communication"]Own block/chip RTL verification for DRAM architectures by defining verification scope, strategy, and plans. Build and maintain SV-UVM verification testbenches and test vectors, run directed and constrained-random regressions, and triage failures. Measure functional/code coverage, identify verification holes, and debug RTL, testbench, and environment issues. Partner with design engineers and international teams to improve verification flows and communicate readiness risks to stakeholders.
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