Subsystem/SoC Level Verification Engineer

Own Ethernet subsystem/SoC level functional verification, designing verification plans and building tests that validate MAC/PCS/SerDes behavior. Develop verification environments using SystemVerilog and UVM, including BFMs, checkers, monitors, and scoreboards. Execute constrained-random verification with code and functional coverage, perform gate-level/SDF simulations, and debug failures to root cause. Work across IP/subsystem/SoC projects using Cadence or Synopsys tools.