Senior Physical Design Engineer

AMD
Markham, Vancouver
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Skills: []

Drive physical implementation for next-generation AMD microprocessor and high-speed IPs within the DXIO FEINT/Implementation team. Own the physical design flow including synthesis, floorplan, placement, clock tree synthesis, routing, and STA closure for complex I/O clocking across protocols like PCIe, SATA, Ethernet, and Infinity Fabric. Develop reference floorplans and implementation scripts (TCL/Python) and support SoCs worldwide to optimize PPA and shorten development schedules.

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FursaFursa
AMD
AMD
13 hours ago

Senior Physical Design Engineer

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Last checked: 2 hours agoStatus: Live

Job Summary

Drive physical implementation for next-generation AMD microprocessor and high-speed IPs within the DXIO FEINT/Implementation team. Own the physical design flow including synthesis, floorplan, placement, clock tree synthesis, routing, and STA closure for complex I/O clocking across protocols like PCIe, SATA, Ethernet, and Infinity Fabric. Develop reference floorplans and implementation scripts (TCL/Python) and support SoCs worldwide to optimize PPA and shorten development schedules.
Location: Markham, Vancouver
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own physical implementation of next-generation IPs through the full physical design flow to achieve best PPA and shorten development schedules.
  • •Support synthesis and DFT, floorplan, placement, clock tree synthesis, routing, and STA closure for very high-speed (>2G) designs with complex I/O clocking.
  • •Work on cutting-edge IP for I/O protocols including PCIe, SATA, Ethernet, and Infinity Fabric link-layer.
  • •Develop reference floorplans and create/maintain implementation scripts for SoCs worldwide.
  • •Collaborate with physical design engineers, RTL design engineers, and NBIO IP team managers to deliver robust implementations.

Key Requirements

  • •Industry experience with synthesis, floor-planning, placement, clock tree synthesis, and post-route timing closure for high-speed (≥2 GHz) designs.
  • •Experience with CDC, PTPX, STA, LINT, and DFT within the physical design flow.
  • •Ability to drive physical implementation through the end-to-end physical design flow (synthesis through STA closure).
  • •Programming/scripting experience in TCL and Python for physical design tasks and automation.
  • •B.E. or M.E. in Electrical or Computer Engineering (or equivalent).
Experience:ASICPhysical designHigh-speed designSoC
Education:
Tech Stack:TCLPythonCDCPTPXSTALINTDFTSynthesisFloorplanningPlacementClock Tree SynthesisRouting

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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