2 days ago

Senior SOC Clocks RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 19 hours agoStatus: Live

Job Summary

Lead the technical implementation of next-generation SoC clocking logic for NVIDIA networking chips, from specification through tape-out and silicon bring-up. Own clock architecture integration (PLL/reference clock, generation/distribution, muxing/dividers, glitchless switching, clock gating, reset synchronization, and CDC). Guide RTL engineers, partner with Physical Design, Design Verification, CAD, DFT, and software/firmware teams, and drive timing/verification closure using RTL and design quality tooling.

Location: Tel Aviv

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Act as technical lead for SoC clocks development, implementing clocking logic from specification through tape-out and bring-up.
•Partner with architecture and micro-architecture teams to define SoC clock and reset schemes and translate them into verifiable RTL.
•Write and review synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing/division, glitchless switching, gating, and reset synchronization.
•Lead and mentor RTL engineers working on clocking, setting coding/quality standards and distributing work across the team.
•Collaborate with Physical Design and Design Verification for clock tree implementation, timing constraints (SDC), debug, test plans, and coverage closure; interact with software/firmware, CAD, Package Design, and DFT.

Key Requirements

•B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
•8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out.
•Demonstrated technical leadership: leading a design area through implementation and tape-out while mentoring engineers and coordinating across teams.
•Expert hands-on RTL design skills in Verilog/SystemVerilog and understanding of RTL impact on synthesis, timing, area, and power.
•Deep understanding of clocking and reset design, including clock gating, clock muxing/dividers, glitchless clock switching, reset synchronization, and clock domain crossing.

Experience:8+ yearsRTL design

Education:Bachelor's in Electrical Engineering or Computer Engineering

Skills:Technical leadershipMentoringCommunicationCross-functional collaborationDesign quality focus

Tech Stack:VerilogSystemVerilogRTLPLLClock generationClock distributionClock muxingClock dividersGlitchless switchingClock gatingReset synchronizationClock domain crossingCDCRDCLintFormal verificationSynthesisStatic timing analysis (STA)SDCDVFS

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

2 days ago

Senior SOC Clocks RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 19 hours agoStatus: Live

Job Summary

Location: Tel Aviv

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Act as technical lead for SoC clocks development, implementing clocking logic from specification through tape-out and bring-up.
•Partner with architecture and micro-architecture teams to define SoC clock and reset schemes and translate them into verifiable RTL.
•Write and review synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing/division, glitchless switching, gating, and reset synchronization.
•Lead and mentor RTL engineers working on clocking, setting coding/quality standards and distributing work across the team.
•Collaborate with Physical Design and Design Verification for clock tree implementation, timing constraints (SDC), debug, test plans, and coverage closure; interact with software/firmware, CAD, Package Design, and DFT.

Key Requirements

•B.Sc./M.Sc. in Electrical Engineering or Computer Engineering.
•8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out.
•Demonstrated technical leadership: leading a design area through implementation and tape-out while mentoring engineers and coordinating across teams.
•Expert hands-on RTL design skills in Verilog/SystemVerilog and understanding of RTL impact on synthesis, timing, area, and power.
•Deep understanding of clocking and reset design, including clock gating, clock muxing/dividers, glitchless clock switching, reset synchronization, and clock domain crossing.

Experience:8+ yearsRTL design

Education:Bachelor's in Electrical Engineering or Computer Engineering

Skills:Technical leadershipMentoringCommunicationCross-functional collaborationDesign quality focus

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor