DFx-DV Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 2,186,520 - 3,123,600 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Teamwork","Analytical skills","Problem-solving"]

Join AMD’s server SOC DFT team to verify next-generation DFT features for EPYC server SOCs. You’ll create and execute test plans, build verification infrastructure in SV/C++, and debug regressions to root-cause design and verification issues. The role includes developing test benches, patterns for post-silicon testing, improving code and functional coverage, and collaborating with cross-site stakeholders across architecture, design, and post-silicon teams.

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FursaFursa
AMD
AMD
21 hours ago

DFx-DV Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Join AMD’s server SOC DFT team to verify next-generation DFT features for EPYC server SOCs. You’ll create and execute test plans, build verification infrastructure in SV/C++, and debug regressions to root-cause design and verification issues. The role includes developing test benches, patterns for post-silicon testing, improving code and functional coverage, and collaborating with cross-site stakeholders across architecture, design, and post-silicon teams.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Create and execute test plans for DFT features for next-generation EPYC server SOCs.
  • •Verify DFT features including JTAG/1500/1687, MBIST, Scan, Fuse, Clocks, Resets, and high-speed IO at SOC level.
  • •Build test benches and verification infrastructure using SV or C++, and develop verification components and pattern generation.
  • •Debug regression failures and root-cause design/verification issues, identify verification gaps, and improve code and functional coverage.
  • •Generate patterns for post-silicon testing, support ATE bring-up, perform post-silicon debugs, and work on emulation platforms.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •Prior experience verifying DFT features at the subsystem/SOC level.
  • •Proficiency with Verilog and/or SystemVerilog plus C/C++ for verification work.
  • •Experience using simulation/debug tools such as VCS and Verdi.
  • •Knowledge of DFT features such as JTAG, Memory BIST, Logic BIST, Scan, and/or ATPG is highly desirable.
  • •Bachelors or Masters degree in Electronics/Electrical Engineering.
Education:Bachelor's in Electronics/Electrical Engineering
Skills:CommunicationTeamworkAnalytical skillsProblem-solving
Languages:En-us
Tech Stack:SystemVerilogSVC++VerilogCJTAG15001687MBISTScanFuseClocksResetsHigh speed IOSV or C++VCSVerdiLinuxWindowsPerl

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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