Senior Principal DFT Design Engineer

Design for Test (DFT) role for SoC/ASIC: develop and execute scan chain insertion, compression scan insertion, MBIST/ LBIST flows, and ATPG to meet design test coverage goals. Drive systematic, quality-metrics-based ATPG pattern generation, debug and analyze failures to improve fault coverage, and verify testbenches by resolving simulation mis-compares. Collaborate across cross-functional stakeholders and deliver DFT tasks independently.