R&D Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Research & Scientific (R&D)Experience: 4-10 yearsSkills: ["Communication","Collaboration"]

As part of the TLR team, you will perform place-and-route and routability analysis to address congestion, and lead physical verification including DRC, LVS, antenna checks, and related chip finishing/tapeout activities. You’ll integrate analog blocks, ensure RC requirements for special/manual signals, and run integrity checks before and after tapeout. You’ll also implement timing ECOs, IR-drop fixes, SPEF extraction, signal EM fixes, and noise analysis using tools like Cadence Innovus and Calibre, with scripting support in Perl/TCL.

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FursaFursa
Broadcom
Broadcom
3 weeks ago

R&D Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 3 weeks ago

Job Summary

As part of the TLR team, you will perform place-and-route and routability analysis to address congestion, and lead physical verification including DRC, LVS, antenna checks, and related chip finishing/tapeout activities. You’ll integrate analog blocks, ensure RC requirements for special/manual signals, and run integrity checks before and after tapeout. You’ll also implement timing ECOs, IR-drop fixes, SPEF extraction, signal EM fixes, and noise analysis using tools like Cadence Innovus and Calibre, with scripting support in Perl/TCL.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Research & Scientific (R&D)
Seniority: Mid level

Key Responsibilities

  • •Perform place-and-route and routability analysis to address congestion as part of the TLR team.
  • •Conduct physical verification including DRC, LVS, antenna, and LUP, covering chip finishing and tapeout activities.
  • •Integrate analog blocks and ensure RC requirements are met for manual/special signals.
  • •Apply integrity checks and manage pre-/post-tapeout eJob view and eJob view release.
  • •Implement timing ECOs and related fixes including IR drop, SPEF extraction, signal EM fixes, and noise analysis.

Key Requirements

  • •4 to 10 years of relevant experience in physical verification and physical design activities.
  • •Proficiency in place-and-route, CTS, routability analysis, and congestion-related analysis.
  • •Hands-on experience with physical verification: DRC, LVS, antenna, LUP, and understanding chip finishing and tapeout workflows.
  • •Working knowledge of Cadence Innovus and Calibre rule decks for DRC/LVS/DFM/DFY, ERC, and ESD latchup.
  • •Scripting experience in Perl and TCL, plus familiarity with timing ECOs, IR drop fixes, SPEF extraction, signal EM fixes, and noise analysis.
Experience:4-10 yearsVLSIPhysical verificationCAD tools
Skills:CommunicationCollaboration
Tech Stack:PerlTCLCalibreCadenceInnovusDRCLVSDFMDFYERCESD latchupAntennaLUPCTSSTAPTSITiming ECOIR dropSPEFSignal EM

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn