IC Design Engineer

Lead Broadcom’s physical design methodology to achieve right-first-time silicon. Own SoC block/level layout activities including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification. Implement timing/functional ECOs and drive P&R, extraction, and verification toward STA closure. Adapt or build automation flows and work with EDA toolchains across P&R, PV, STA, and ECO stages for advanced nodes like 5nm and below.