Memory Layout Technical Leader

Cisco
Yerevan
Workplace: HybridFull timeFunction: Administration & Executive AssistanceExperience: 10+ yearsEducation: mastersSkills: ["Technical leadership","Mentorship","Analytical problem-solving","Cross-functional communication","Stakeholder influence"]

Lead memory layout implementation for Cisco Silicon One, driving physical design strategy for high-performance memory and SRAM blocks. Architect complex layout solutions, provide technical leadership, and run post-layout validation cycles to ensure silicon reliability and integration across multi-module subsystems. Improve layout automation frameworks to cut iteration time and increase design velocity, delivering scalable, high-integrity components for next-generation Cisco networking hardware.

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FursaFursa
Cisco
Cisco
1 day ago

Memory Layout Technical Leader

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Job Summary

Lead memory layout implementation for Cisco Silicon One, driving physical design strategy for high-performance memory and SRAM blocks. Architect complex layout solutions, provide technical leadership, and run post-layout validation cycles to ensure silicon reliability and integration across multi-module subsystems. Improve layout automation frameworks to cut iteration time and increase design velocity, delivering scalable, high-integrity components for next-generation Cisco networking hardware.
Location: Yerevan
Workplace: Hybrid
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Drive physical design strategy for high-performance memory and SRAM blocks aligned to power, performance, and area targets.
  • •Architect complex layout solutions and provide technical leadership to elevate team proficiency.
  • •Execute post-layout validation cycles to ensure silicon-level reliability and integration across multi-module subsystems.
  • •Lead efforts to enhance layout automation frameworks to reduce design iteration time and increase total velocity.
  • •Deliver high-integrity, scalable silicon components that enable next-generation Cisco networking hardware.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •10+ years of physical design/layout experience with 3+ years hands-on SRAM layout implementation.
  • •Expert proficiency with industry-standard EDA tools such as Cadence or Synopsys.
  • •Experience with advanced node technologies including TSMC 22nm, 12nm, 7nm, 5nm, or 2nm.
Experience:10+ yearsEDASemiconductorSilicon designSRAM layout
Education:Master's
Skills:Technical leadershipMentorshipAnalytical problem-solvingCross-functional communicationStakeholder influence
Tech Stack:SRAMMemory layoutPhysical designEDACadenceSynopsysTclPythonTSMC 22nmTSMC 12nmTSMC 7nmTSMC 5nmTSMC 2nmEM/IR closureEM/IR

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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