Principal Software Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["C++","SystemC","TLM","Python"]

We are seeking modeling engineers to develop cycle-level performance models for next-generation DDR memory controller architectures, perform architectural tradeoff analysis, and enable data-driven design decisions. The role involves hardware modeling using C/C++, SystemC/TLM/Python, collaboration with Memory Architects, and creating synthetic memory traffic traces to analyze throughput and latency across various scenarios.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
6 months ago

Principal Software Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 3 years ago

Job Summary

We are seeking modeling engineers to develop cycle-level performance models for next-generation DDR memory controller architectures, perform architectural tradeoff analysis, and enable data-driven design decisions. The role involves hardware modeling using C/C++, SystemC/TLM/Python, collaboration with Memory Architects, and creating synthetic memory traffic traces to analyze throughput and latency across various scenarios.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Develop cycle-level performance models in SystemC or C++
  • •Correlate performance models to match RTL configurations and traffic conditions
  • •Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
  • •Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • •Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • •Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Key Requirements

  • •BE/B.Tech or ME/M.Tech in ECE, E&Tc, CS or similar
  • •5+ years of experience in hardware modeling, functional or performance
  • •Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • •Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
  • •Experience with hardware modeling for DDR memory/controller architecture (desirable)
Experience:5+ yearsSemiconductorHardwareSoC
Education:Bachelor's
Skills:C++SystemCTLMPython
Languages:English
Tech Stack:C++SystemCTLMPython

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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