Sr. Manager Silicon Design Engineering

AMD
Santa Clara
Workplace: RemoteFull timeUSD 187,600 - 321,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: mastersSkills: ["Leading","Team management","Cross-functional collaboration","Technical guidance"]

Develop and lead timing closure methodologies and strategies for SoC and IP blocks, overseeing STA closure for complex chip designs with chiplet and 3D stack interfaces. Own global clock tree construction and analysis, set timing targets, and partner with design teams to secure PPA and performance sign-offs. Lead and manage engineering efforts, manage physical design closure (floorplanning, placement, CTS, routing), and support post-silicon debugging of timing issues.

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FursaFursa
AMD
AMD
3 days ago

Sr. Manager Silicon Design Engineering

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Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Develop and lead timing closure methodologies and strategies for SoC and IP blocks, overseeing STA closure for complex chip designs with chiplet and 3D stack interfaces. Own global clock tree construction and analysis, set timing targets, and partner with design teams to secure PPA and performance sign-offs. Lead and manage engineering efforts, manage physical design closure (floorplanning, placement, CTS, routing), and support post-silicon debugging of timing issues.
Location: Santa Clara
Workplace: Remote
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Develop and establish timing closure methodologies and strategies for SoC and IP blocks, ensuring compliance with requirements.
  • •Oversee STA closure for complex SoC designs featuring chiplet and 3D stack interfaces.
  • •Own global clock tree construction and analysis and refine clocking to meet performance, power, and area targets.
  • •Manage physical design closure activities including floorplanning, placement, CTS, routing, and timing closure.
  • •Manage silicon design projects and lead an engineering team, providing technical guidance and supporting post-silicon debugging of timing issues.

Pay and Benefits

Salary: USD 187,600 - 321,600 annually

Key Requirements

  • •Master’s degree (or foreign equivalent) in Electronics Engineering, Computer Science, Computer Engineering, Electrical Engineering, or related field.
  • •4 years of experience in the job offered or a closely related engineering role (or alternatively, a Bachelor’s degree with 6 years).
  • •Use Computer-Aided Design (CAD) tools to oversee the chip design process, including physical design of deep submicron digital ASICs.
  • •Oversee ASIC static timing analysis (STA) closure to ensure the design functions correctly at target speed.
  • •Scripting experience in TCL, Perl, or Python to automate repetitive design steps (e.g., synthesis, timing analysis, or place-and-route).
Experience:4+ years
Education:Master's in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering (or related field)
Skills:LeadingTeam managementCross-functional collaborationTechnical guidance
Languages:En-us
Tech Stack:Computer-Aided Design (CAD)ASIC design toolsSynthesisSimulationEquivalence checkingStatic timing analysis (STA)Electronic Design Automation (EDA)TCLPerlPythonPlace-and-routeGlobal clock tree constructionPhysical design closureFloor planningClock tree synthesis (CTS)Routing

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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