Staff/Principal, APTD CEM - Advanced Packaging Wafer Level Technology Engineering
Singapore
Workplace: OnsiteFull timeFunction: Communications, PR & CommunitySkills: ["Analytical thinking","Problem-solving","Communication","Leadership","Cross-functional collaboration"]Develop and improve post-fab, wafer-level finishing processes for high-performance memory packaging, driving performance, cost, manufacturability, quality, reliability, and schedule outcomes. Establish wafer thinning and backside metal interconnect process technologies, evaluate equipment and materials, and advance quality via measurement, inspection, testing, SPC/DOE, and defect analysis. Coordinate with multiple engineering teams to transfer process of record/model of record documentation into high-volume manufacturing.
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