Intel

1 month ago

Senior Mixed Signal Validation and Debug Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Join Intel's Hard IP Development Group to validate and debug mixed-signal IP across pre-silicon and post-silicon stages. Collaborate with SOC customers and IP design teams, perform IP enablement during SOC Power Ons, and lead post-silicon investigations to root cause silicon issues, leveraging AI-driven tools and Python scripting in a fast-paced environment.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Work closely with SOC customers and IP design teams to provide pre silicon to post silicon IP design characterizations, generating test plans and test contents using AI driven tools and pythonSV scripting, SOC board design reviews and recommendations, signal and power integrity simulations and post silicon debugs.
•Represent the IP team during SOC Power Ons for test chips and products and provide hands on IP enabling support
•Identify IP related silicon issues, investigate, debug and disposition customer bugs/sightings in a timely manner
•Carry out pre silicon and post silicon reproduction of the issue and work towards root cause with failure analysis
•Lead IP debug when required and contribute to design/verification improvements to prevent recurrence

Key Requirements

•Must have a BS or MS or PhD in Computer Engineering or Electrical Engineering or a Related Field.
•Minimum 6+ years of experience in Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die).
•Well versed with the lab hardware and software; proficient in using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs.
•Familiarity with IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet; PHY or Controller experience acceptable.
•Able to lead on IP debug and have a good understanding of signal integrity and power delivery (plus pre silicon design or simulation experience)

Experience:6+ yearsSemiconductorElectrical engineeringPost-silicon validation

Education:Bachelor's in Electrical Engineering

Skills:CommunicationProblem-solvingTeamworkDebuggingLab skills

Languages:English

Tech Stack:PythonOscilloscopeLogic AnalyzerBERTPCIeUSBDDRLPDDRDie2DieEthernetUSB Type-CUCIeAI-driven tools

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 month ago

Senior Mixed Signal Validation and Debug Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Work closely with SOC customers and IP design teams to provide pre silicon to post silicon IP design characterizations, generating test plans and test contents using AI driven tools and pythonSV scripting, SOC board design reviews and recommendations, signal and power integrity simulations and post silicon debugs.
•Represent the IP team during SOC Power Ons for test chips and products and provide hands on IP enabling support
•Identify IP related silicon issues, investigate, debug and disposition customer bugs/sightings in a timely manner
•Carry out pre silicon and post silicon reproduction of the issue and work towards root cause with failure analysis
•Lead IP debug when required and contribute to design/verification improvements to prevent recurrence

Key Requirements

•Must have a BS or MS or PhD in Computer Engineering or Electrical Engineering or a Related Field.
•Minimum 6+ years of experience in Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die).
•Well versed with the lab hardware and software; proficient in using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs.
•Familiarity with IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet; PHY or Controller experience acceptable.
•Able to lead on IP debug and have a good understanding of signal integrity and power delivery (plus pre silicon design or simulation experience)

Experience:6+ yearsSemiconductorElectrical engineeringPost-silicon validation

Education:Bachelor's in Electrical Engineering

Skills:CommunicationProblem-solvingTeamworkDebuggingLab skills

Languages:English

Tech Stack:PythonOscilloscopeLogic AnalyzerBERTPCIeUSBDDRLPDDRDie2DieEthernetUSB Type-CUCIeAI-driven tools

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor