Lead Analog Layout Design Engineer

Cadence Design Systems
Cork
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsSkills: ["Technical leadership","Problem-solving","Communication","Teamwork"]

Lead analog layout design for SERDES/UCie products on a PMA custom layout team in Cork. Own technical leadership across the back-end flow, from floor planning and detailed layout to final verification against foundry design rules, supporting PHY top-level integration and sign-off. Collaborate with circuit designers and global teams across time zones to deliver high-quality layouts for analog/mixed-signal blocks at data rates up to 64 Gbps.

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Cadence Design Systems
Cadence Design Systems
22 hours ago

Lead Analog Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Lead analog layout design for SERDES/UCie products on a PMA custom layout team in Cork. Own technical leadership across the back-end flow, from floor planning and detailed layout to final verification against foundry design rules, supporting PHY top-level integration and sign-off. Collaborate with circuit designers and global teams across time zones to deliver high-quality layouts for analog/mixed-signal blocks at data rates up to 64 Gbps.
Location: Cork
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Provide technical leadership for the PMA custom layout design team for SERDES UCie products, including PHY top-level integration and sign-off.
  • •Design high-speed SERDES with analog/mixed-signal circuit block quality layouts for data rates up to 64 Gbps on leading-edge technology nodes.
  • •Own back-end layout flow end-to-end, from initial floor planning through detailed layout and final verification for foundry design rule conformance.
  • •Collaborate with circuit designers to deliver analog/mixed-signal layouts that meet technical requirements and schedule needs.
  • •Coordinate with global teams across multiple time zones to ensure successful layout design and verification outcomes.
Travel: Medium travel

Key Requirements

  • •Minimum 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development.
  • •Proficient layout experience across key SERDES blocks (e.g., driver, receiver, serializer/deserializer, PLL, clock distribution, bias/bandgap, voltage regulators).
  • •Ability to implement high-speed, high-accuracy cells/blocks/IP with timely, high-quality, efficient execution.
  • •Experience working with custom layout designers globally to build high-quality IP and test chips.
  • •BEng, MEng or PhD.
Experience:7+ yearsSemiconductorsCMOS SERDESHigh-speed I/OAnalog/mixed-signal
Skills:Technical leadershipProblem-solvingCommunicationTeamwork
Tech Stack:SERDESUCieCMOSHigh-speed I/O2nm FinFETFloor planningFoundry design rulesPLLLow jitter PLLClock distributionVirtuosoPVS

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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