3 months ago

Staff Silicon Photonics Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Experienced silicon photonics designer responsible for end-to-end design, simulation, layout, and characterization of passive silicon photonic components for high-performance AI inference applications, collaborating with foundries and cross-functional teams to bring photonic designs from concept to production-ready silicon.

Location: San Mateo

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design, simulate, and optimize passive silicon photonic building blocks: edge couplers, grating couplers, and hybrid/directional/multimode-interference couplers for compact PIC designs.
•Develop waveguide routing, splitters, polarization splitters/rotators, crossings, and other PIC sub-elements with attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
•Conduct FDTD, eigenmode expansion, and circuit-level simulations using industry tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
•Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow; generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
•Manage and drive tapeout processes with mainstream SiPh foundries or equivalent silicon photonics PDKs; interface with foundry process engineers to negotiate design rule waivers and resolve integration challenges.
•Define and execute design-of-experiments test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.

Pay and Benefits

Salary: USD 230,000 - 280,000 annually

Equity and Bonus:Equity

Perks:Health InsurancePaid Leave401kEquityDentalVisionLife InsuranceHospital InsuranceCritical IllnessAccident Insurance

Key Requirements

•M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
•3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record)
•Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms
•Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation
•Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation

Experience:3+ yearsSilicon photonicsPhotonicsSemiconductorsAI hardware

Education:Master's

Skills:Problem-solvingCollaborationAttention to detailCommunication

Languages:English

Tech Stack:Ansys LumericalSynopsys OptsimCadence VirtuosoKLayoutGDSFactoryIPKISSPythonMATLABFDTDEMEPPIGDSII

Company Brief

Neurophos

Develops metamaterial-based photonic optical processing units (OPUs) to deliver high-performance, energy-efficient AI inference chips for datacenters, aiming to scale photonic compute to exaflop levels.

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn

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Neurophos

3 months ago

Staff Silicon Photonics Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: San Mateo

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design, simulate, and optimize passive silicon photonic building blocks: edge couplers, grating couplers, and hybrid/directional/multimode-interference couplers for compact PIC designs.
•Develop waveguide routing, splitters, polarization splitters/rotators, crossings, and other PIC sub-elements with attention to insertion loss, return loss, bandwidth, polarization dependence, and process variation tolerance.
•Conduct FDTD, eigenmode expansion, and circuit-level simulations using industry tools; perform tolerance and process-corner analysis to ensure robust yield across foundry runs.
•Implement PIC layouts using Cadence Virtuoso, KLayout, or script-based parametric design flow; generate DRC-clean GDS for submission to foundry, including DRC/LVS sign-off, design review, and mask data preparation.
•Manage and drive tapeout processes with mainstream SiPh foundries or equivalent silicon photonics PDKs; interface with foundry process engineers to negotiate design rule waivers and resolve integration challenges.
•Define and execute design-of-experiments test chip strategies to characterize process sensitivities and close the loop between simulation and measurement results.

Pay and Benefits

Salary: USD 230,000 - 280,000 annually

Equity and Bonus:Equity

Perks:Health InsurancePaid Leave401kEquityDentalVisionLife InsuranceHospital InsuranceCritical IllnessAccident Insurance

Key Requirements

•M.S. or Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline
•3+ years of hands-on silicon photonics design experience in an industry setting (or equivalent depth of graduate research with demonstrated tapeout and measurement record)
•Proven expertise in designing passive silicon photonic components: edge couplers, grating couplers, directional/hybrid couplers, waveguides, and splitters on SOI platforms
•Proficiency with photonic simulation tools: FDTD, BPM, FDE, CMT, and EME solvers (Ansys Lumerical Suite, Synopsys Rsoft, Photon Design, or equivalent) and circuit-level simulation
•Demonstrated PIC layout experience using Cadence Virtuoso, KLayout, and/or Python-based parametric layout frameworks (GDSFactory, IPKISS, or similar) for GDS generation

Experience:3+ yearsSilicon photonicsPhotonicsSemiconductorsAI hardware

Education:Master's

Skills:Problem-solvingCollaborationAttention to detailCommunication

Languages:English

Tech Stack:Ansys LumericalSynopsys OptsimCadence VirtuosoKLayoutGDSFactoryIPKISSPythonMATLABFDTDEMEPPIGDSII

Company Brief

Neurophos

Industry: Deep Tech

Company Size: Small (11 to 50 employees)

Growth: Growth Stage Startup

Funding: Series A

Headquarters: Austin, United States

Founded: 2020

Website LinkedIn