SpaceX

1 month ago

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Develop and optimize next-generation silicon for SpaceX Starlink by performing partition synthesis, physical implementation, and signoff across RTL-to-GDSII flows. Collaborate with ASIC teams to drive architectural feasibility, timing, power and area targets, and troubleshoot design issues to deliver high-performance, space-grade silicon used in satellite and ground systems.

Location: Austin, Irvine, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
•Develop/improve physical design methodologies and automation scripts for various implementation steps.
•Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
•Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
•Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering or computer science.
•5+ years of ASIC and/or physical design flow development experience in industry.
•Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows.
•Knowledge of deep sub-micron FinFET and CMOS solid state physics.
•Good scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.).

Experience:5+ yearsASICPhysical designRTL2GDSIISignoff flowsEDA tools

Education:Bachelor's

Skills:RTL2GDSIIEDA toolsScriptingPythonTCLPerlBashMakefileCMOSFinFETDFT/Scan/MBIST/LBIST

Languages:English

Tech Stack:ASICRTLGDSIISTAElectromigrationVoltage dropTimingPowerAreaElectrical engineeringCMOSFinFET

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

1 month ago

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 12 hours agoStatus: Live

Job Summary

Location: Austin, Irvine, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Sr. Manager level

Key Responsibilities

•Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks).
•Develop/improve physical design methodologies and automation scripts for various implementation steps.
•Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs.
•Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
•Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering or computer science.
•5+ years of ASIC and/or physical design flow development experience in industry.
•Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows.
•Knowledge of deep sub-micron FinFET and CMOS solid state physics.
•Good scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.).

Experience:5+ yearsASICPhysical designRTL2GDSIISignoff flowsEDA tools

Education:Bachelor's

Skills:RTL2GDSIIEDA toolsScriptingPythonTCLPerlBashMakefileCMOSFinFETDFT/Scan/MBIST/LBIST

Languages:English

Tech Stack:ASICRTLGDSIISTAElectromigrationVoltage dropTimingPowerAreaElectrical engineeringCMOSFinFET

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn