Senior ASIC Physical Design Engineer

AMD
Bengaluru
Full timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Analytical skills","Communication skills","Team player","Attention to details","Problem-solving"]

Lead physical design for next-generation ASICs within AMD’s AECG organization, driving RTL-to-GDS2 implementation and optimizing power/area/performance for high-performance solutions. Work closely with customer and SOC architects, the CAD team, and design teams to execute floorplanning, power-plan implementation, synthesis, placement, CTS, routing, timing closure, extraction, and physical verification/sign-off. Hands-on tool usage and flow development scripting are central to the role.

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FursaFursa
AMD
AMD
6 days ago

Senior ASIC Physical Design Engineer

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Job Summary

Lead physical design for next-generation ASICs within AMD’s AECG organization, driving RTL-to-GDS2 implementation and optimizing power/area/performance for high-performance solutions. Work closely with customer and SOC architects, the CAD team, and design teams to execute floorplanning, power-plan implementation, synthesis, placement, CTS, routing, timing closure, extraction, and physical verification/sign-off. Hands-on tool usage and flow development scripting are central to the role.
Location: Bengaluru
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive physical design for next-generation ASICs, meeting engineering, business, and customer requirements.
  • •Implement the RTL-to-GDS2 flow, including floorplanning, power-plan physical implementation, synthesis, placement, CTS, routing, extraction, and physical verification.
  • •Handle full-chip level floorplanning and planning activities such as bus/pin planning, feed-thru planning, and related optimization.
  • •Run timing and physical sign-off steps, including static timing analysis, DRC/LVS, crosstalk analysis, EM/IR, and formal equivalence checks.
  • •Use multiple PNR tools and contribute to hands-on flow development and scripting for design flow improvement.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years of professional experience in ASIC physical design with RTL-to-GDS development and leading understanding of the flow.
  • •Experience driving physical design optimization for industry-leading performance/area and performance/power.
  • •Strong background in automated synthesis and timing-driven place and route for high-speed datapath and control logic.
  • •Hands-on experience with floorplanning, PPA-related power/clock techniques (clock tree synthesis, gating, scan stitching), and design optimization for timing/power/area and cycle time reduction.
  • •BS or MS in Electrical Engineering or Computer Science (or equivalent).
Experience:8+ yearsASIC physical designHigh performance designsRTL-to-GDSAutomated place and routeFinFETDual patterning
Education:Master's in Electrical Engineering or Computer Science
Skills:Analytical skillsCommunication skillsTeam playerAttention to detailsProblem-solving
Tech Stack:RTL to GDS2FloorplanningPower planSynthesisPlacementCTSTiming ClosureRoutingExtractionPhysical VerificationDRC & LVSCrosstalk AnalysisEM/IRFormal EquivalencePNRSynopsys Fusion CompilerICC2Design CompilerPrimeTimeStarRC

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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