Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12-14 yearsEducation: bachelorsSkills: ["Problem-solving","Communication","Attention to detail"]

Senior VLSI design engineer focusing on Verilog and HVL-based verification, UVM/OVM/eRM methodologies, and assertion/coverage closure. Lead test-bench development, RTL/GLS debug, and automation scripting (Perl/Tcl). Expected to manage project schedules and deliverables in a high-performance hardware design environment.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Senior VLSI design engineer focusing on Verilog and HVL-based verification, UVM/OVM/eRM methodologies, and assertion/coverage closure. Lead test-bench development, RTL/GLS debug, and automation scripting (Perl/Tcl). Expected to manage project schedules and deliverables in a high-performance hardware design environment.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead verification and design activities for VLSI projects, collaborating with RTL/design teams to meet schedules and deliverables
  • •Develop and maintain test-benches and verification environments using UVM/OVM/eRM methodologies
  • •Create and close assertions, constraints, coverages, and formal verification strategies
  • •Debug RTL/GLS simulations and diagnose issues in complex test-benches
  • •Automate common workflows and scripting tasks using Perl/Tcl to improve efficiency

Key Requirements

  • •12-14 years of work experience in the VLSI domain with a Master’s or bachelor’s degree in engineering
  • •Strong expertise in Verilog and HVL (SV, Specman e) with UVM/OVM/eRM methodology
  • •Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification
  • •Expertise in test-bench development
  • •Strong RTL and GLS (with or without SDF) sim debug skills; ability to manage project schedule and delivery independently
Experience:12-14 yearsVLSISemiconductorHardware design
Education:Bachelor's in Engineering
Skills:Problem-solvingCommunicationAttention to detail
Tech Stack:VerilogHVLSVSpecman eUVMOVMERMAssertionsTest-benchRTLGLSSDFPerlTcl

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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