Senior DFT Engineer

Own and deliver Design-for-Test (DFT) engineering for complex semiconductor chips, collaborating cross-functionally to implement test access mechanisms, IO BIST, memory BIST, and scan compression. Develop and deploy DFT methodologies for next-generation products, validate test patterns and logic with strong analytical rigor using vendor tools, and support silicon debug and ATE bring-up. Mentor junior engineers on test design trade-offs across cost and quality.