DRAM Design Tech Layout Engineer

Micron Technology
Mexico
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["Leadership","Problem-solving","Communication","Teamwork","Multi-tasking"]

Translate DRAM schematics into layout used for creating fabrication reticules, ensuring assigned DRAM products meet engineering and process criteria. Lead and deliver IP layout development with strong quality verification (LVS/DRC/EM), documentation, and on-time block-level layout delivery. Plan area/time estimates, scheduling, delegation, and issue-resolution methodologies while collaborating with global Design and engineering teams to optimize routing, yield, and reliability.

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FursaFursa
Micron Technology
Micron Technology
2 weeks ago

DRAM Design Tech Layout Engineer

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Last checked: 14 hours agoStatus: Live

Job Summary

Translate DRAM schematics into layout used for creating fabrication reticules, ensuring assigned DRAM products meet engineering and process criteria. Lead and deliver IP layout development with strong quality verification (LVS/DRC/EM), documentation, and on-time block-level layout delivery. Plan area/time estimates, scheduling, delegation, and issue-resolution methodologies while collaborating with global Design and engineering teams to optimize routing, yield, and reliability.
Location: Mexico
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop and deliver IP layouts used in DRAM chips, translating schematics into layout for fabrication reticules.
  • •Perform layout verification (LVS/DRC/EM), quality checks, and documentation.
  • •Ensure on-time delivery of block-level layouts with acceptable quality across multiple project environments.
  • •Plan and manage area/time estimation, scheduling, delegation, and execution to meet project deadlines and breakthroughs.
  • •Guide team members in sub block-level layout execution and review; collaborate with Design and global teams to ensure layout success.

Key Requirements

  • •BE/BTech or MTech in Electronic/VLSI Engineering (or exceptionally talented Diploma holders in electronic/VLSI).
  • •3+ years of experience in layout designs in advanced CMOS process.
  • •Ability to perform IP layout development and physical verification activities for complex designs.
  • •Expertise in layout area/routing optimization, design rules, yield, and reliability issues.
  • •Strong understanding of layout fundamentals (e.g., electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis) and problem-solving for verification.
Experience:3+ yearsCMOSVLSISemiconductors
Education:Bachelor's in Electronic/VLSI Engineering
Skills:LeadershipProblem-solvingCommunicationTeamworkMulti-tasking
Tech Stack:Cadence Virtuoso schematic editorCadence Virtuoso layoutMentor CalibreLVSDRCEMMask generationTapeout

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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