IOMMU Design Verification Engineer
AMD
Vancouver
Workplace: HybridFull timeCAD 112,000 - 192,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","UVM","C","C++","Linux","Windows"]ASIC design verification engineer for AMD’s IOHUB NBIO team, responsible for defining verification architecture, test plans, verification environment, and end-to-end ownership of IP verification. Collaborate with IP architects, develop VIP/testcases in SystemVerilog/UVM, and drive regression, coverage, and verification closure in a fast-paced multi-project setting.

