ASIC Verification Engineer

ASIC Verification Engineer for NVIDIA's GPU clocking group. Responsible for developing test plans, verification infrastructure, and a SV/UVM-based verification environment to validate high-speed clocking logic across functional, DFT, circuit, power, and physical design constraints. Collaborates with architects, designers, and post-silicon teams to drive verification closure and methodology development, enabling reliable clocking for GPUs from consumer graphics to AI workloads.