NVIDIA

2 days ago

Senior Software R&D Engineer, VLSI Physical Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 day agoStatus: Live

Job Summary

Develop and improve optimization engines for VLSI physical design, co-optimizing steps like legalization and sizing to increase chip frequency while minimizing power. Build algorithms in C++ for gate-level sizing, buffering, clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction. Collaborate end-to-end from invention to deployment inside design teams, using tools and flows for modern hardware and AI chip development.

Location: Santa Clara, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Invent new optimization engines that fuse independent physical design engines to improve chip frequency and power across internal optimization tools.
•Improve C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
•Own the end-to-end process from discovery and invention through implementation and deployment within design teams.
•Enable deployment by integrating solutions directly with physical design workflows and teams.
•Collaborate across multiple technical areas to advance high-capacity timing closure and improve PPA outcomes.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually

Equity and Bonus:Equity

Key Requirements

•BS, MS, PhD (or equivalent) in Electrical Engineering or Computer Science.
•6+ years developing VLSI physical design algorithms using C++.
•Strong understanding of VLSI timing optimization concepts (e.g., cell libraries, interconnect models, crosstalk, IR drop, timing constraints, corners, congestion).
•Experience with design implementation tools including ICC2, Innovus, PrimeTime, Tempus, and StarRC, plus design flow scripting in Perl, Tcl, and Python.
•Strong communication and interpersonal skills.

Experience:VLSIPhysical designEDAHardwareMachine learning

Skills:CommunicationInterpersonal skills

Tech Stack:C++C++14LambdasConcurrencyMultithreadingDistributed computingEfficient memoryI/OICC2InnovusPrimeTimeTempusStarRCPerlTclPythonReinforcement learningGNNsGraph Neural Networks

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

2 days ago

Senior Software R&D Engineer, VLSI Physical Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 day agoStatus: Live

Job Summary

Location: Santa Clara, Austin

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Invent new optimization engines that fuse independent physical design engines to improve chip frequency and power across internal optimization tools.
•Improve C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
•Own the end-to-end process from discovery and invention through implementation and deployment within design teams.
•Enable deployment by integrating solutions directly with physical design workflows and teams.
•Collaborate across multiple technical areas to advance high-capacity timing closure and improve PPA outcomes.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually

Equity and Bonus:Equity

Key Requirements

•BS, MS, PhD (or equivalent) in Electrical Engineering or Computer Science.
•6+ years developing VLSI physical design algorithms using C++.
•Strong understanding of VLSI timing optimization concepts (e.g., cell libraries, interconnect models, crosstalk, IR drop, timing constraints, corners, congestion).
•Experience with design implementation tools including ICC2, Innovus, PrimeTime, Tempus, and StarRC, plus design flow scripting in Perl, Tcl, and Python.
•Strong communication and interpersonal skills.

Experience:VLSIPhysical designEDAHardwareMachine learning

Skills:CommunicationInterpersonal skills

Tech Stack:C++C++14LambdasConcurrencyMultithreadingDistributed computingEfficient memoryI/OICC2InnovusPrimeTimeTempusStarRCPerlTclPythonReinforcement learningGNNsGraph Neural Networks

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor