2 months ago

Sr. Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Lead verification strategies for SOCs/Chiplet-based SOCs at Cadence, driving complete SOC level verification cycles with SV/UVM-based environments. Mentor engineers, define test plans, and collaborate across design, architecture, and cross-functional teams to deliver high-quality verification across complex IPs and subsystems.

Location: Hyderabad

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead verification strategy and high-quality execution for SOCs/Chiplet-based SOCs.
•Mentor and guide verification engineers, fostering technical excellence.
•Collaborate with design, architecture, and cross-functional teams to ensure seamless verification cycles for complex IP/SOC projects.
•Develop test plans, tests, and verification environments using SV/UVM methodologies.
•Ensure coverage-driven verification closure across the complete SOC verification cycle.

Key Requirements

•BTech/ MTech in Engineering
•12+ years of VLSI industry experience in Verification
•SOC level verification experience preferred
•IP or Subsystem or SOC level verification experience
•Strong knowledge of SV, UVM; ability to create verification environment using UVM methodology

Experience:12+ yearsVLSIVerificationSOCIPSubsystem

Education:Bachelor's

Skills:SVUVMVerificationTest plansDebugProblem solving

Tech Stack:SVUVMVerification environmentBus functional modelsMonitorsCheckersScoreboards

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

2 months ago

Sr. Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Hyderabad

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Lead verification strategy and high-quality execution for SOCs/Chiplet-based SOCs.
•Mentor and guide verification engineers, fostering technical excellence.
•Collaborate with design, architecture, and cross-functional teams to ensure seamless verification cycles for complex IP/SOC projects.
•Develop test plans, tests, and verification environments using SV/UVM methodologies.
•Ensure coverage-driven verification closure across the complete SOC verification cycle.

Key Requirements

•BTech/ MTech in Engineering
•12+ years of VLSI industry experience in Verification
•SOC level verification experience preferred
•IP or Subsystem or SOC level verification experience
•Strong knowledge of SV, UVM; ability to create verification environment using UVM methodology

Experience:12+ yearsVLSIVerificationSOCIPSubsystem

Education:Bachelor's

Skills:SVUVMVerificationTest plansDebugProblem solving

Tech Stack:SVUVMVerification environmentBus functional modelsMonitorsCheckersScoreboards

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor