Lead Software Engineer - Logic Synthesis

Develop and maintain the Palladium synthesizer, adding support for new VHDL/Verilog features and improving logic optimization and performance. Work on RTL design modeling using Verilog/SystemVerilog, VHDL, or SysC, and contribute to verification practices using UVM and SC/TLM. Collaborate across a multi-site, multi-person project while applying EDA/CAD or logic verification expertise.