Sr. Principal Software Engineer, Physical Verification

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 161,000 - 299,000 annuallyFunction: Software EngineeringExperience: 10+ yearsEducation: mastersSkills: ["Problem-solving","Written communication","Verbal communication","Collaboration"]

Build and implement robust physical verification software for advanced semiconductor devices at leading-edge semiconductor nodes. Validate, maintain, and document solutions to ensure reliability and accuracy, while solving complex mathematical and geometric verification challenges. Collaborate with a geographically distributed R&D team through technical discussions, code reviews, and continuous process improvements, contributing to the development and validation of next-generation chip design and manufacturing tools.

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Cadence Design Systems
Cadence Design Systems
11 hours ago

Sr. Principal Software Engineer, Physical Verification

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Build and implement robust physical verification software for advanced semiconductor devices at leading-edge semiconductor nodes. Validate, maintain, and document solutions to ensure reliability and accuracy, while solving complex mathematical and geometric verification challenges. Collaborate with a geographically distributed R&D team through technical discussions, code reviews, and continuous process improvements, contributing to the development and validation of next-generation chip design and manufacturing tools.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Design, develop, and implement software for physical verification of advanced semiconductor devices
  • •Validate, maintain, and document software solutions to ensure reliability and accuracy
  • •Solve complex mathematical and geometric challenges related to semiconductor verification
  • •Collaborate with global team members in a distributed environment to deliver high-quality results
  • •Participate in technical discussions, code reviews, and process improvements

Pay and Benefits

Salary: USD 161,000 - 299,000 annually
Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

  • •Master’s degree in Computer Science or Computer Engineering and 10+ years of work experience
  • •Strong proficiency in C and C++ programming languages
  • •Solid problem-solving skills to tackle technical challenges
  • •Effective written and verbal communication skills for cross-team collaboration
Experience:10+ yearsSemiconductorsR&DPhysical verificationComputational geometry
Education:Master's in Computer Science or Computer Engineering
Skills:Problem-solvingWritten communicationVerbal communicationCollaboration
Tech Stack:CC++

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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