SerDes Verification Engineer
Singapore
Workplace: HybridFull timeSGD 50,400 - 72,000 annuallyFunction: Solutions Engineering & Sales EngineeringEducation: mastersSkills: ["Analytical","Problem-solving","Communication","Collaboration"]Verify and validate high-speed SerDes interfaces for advanced SoCs and chiplet designs. Build UVM/SystemVerilog (and related HDL) testbenches, run simulations, and debug timing, protocol, and performance issues. Evaluate signal integrity, jitter, BER, and eye diagrams, and ensure compliance with protocols such as UCIe, PCIe, Ethernet, USB, DDR, and DisplayPort. Develop automated regressions, collaborate across design and hardware teams, and document results.
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