RTL Design Lead Engineer
Anywhere
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Verilog","SystemVerilog","VHDL","Lint","CDC","DFT","VCS","NCsim","Verdi","Spyglass","Timing analysis","ECO","Magillem","DC","SDC","PCIe","NVMe","UFS","FPGA"]Lead the design and RTL development of storage IPs (NVMe, UFS, PCIe, CXL) for Samsung SSIR, guiding architecture, verification interfaces, and timing constraints. Manage cross-functional collaboration with verification, validation, SoC, and FW teams, optimize synthesis, area and power, and drive ECOs and timing analyses for high-performance storage controllers.
