Lead Staff Engineer, Layout Design

Micron Technology
Mexico
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsSkills: ["Communication","Stakeholder management","Mentoring","Team leadership","Quality oversight"]

Lead a distributed team delivering complex analog, mixed-signal, and custom semiconductor layouts for next-generation AI and high-performance computing solutions. Own block-level layout schedules and planning across concurrent projects, ensure layout verification quality (LVS, DRC, antenna checks), and perform deep sub-block reviews. Mentor layout engineers of all levels, coordinate with global engineering teams for full-chip integration, and drive timely, high-quality tapeout readiness.

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FursaFursa
Micron Technology
Micron Technology
2 months ago

Lead Staff Engineer, Layout Design

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Lead a distributed team delivering complex analog, mixed-signal, and custom semiconductor layouts for next-generation AI and high-performance computing solutions. Own block-level layout schedules and planning across concurrent projects, ensure layout verification quality (LVS, DRC, antenna checks), and perform deep sub-block reviews. Mentor layout engineers of all levels, coordinate with global engineering teams for full-chip integration, and drive timely, high-quality tapeout readiness.
Location: Mexico
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead a team designing and developing critical analog, mixed-signal, and custom block layouts, including support for full-chip-level integration.
  • •Oversee layout verification activities including LVS, DRC, antenna checks, documentation, and quality reviews.
  • •Ensure timely, high-quality delivery of block-level layouts that meet project requirements.
  • •Coordinate planning, area/time estimation, scheduling, task delegation, and execution for multiple concurrent projects.
  • •Perform detailed reviews of sub-block-level layouts and collaborate with global engineering teams to align execution across Micron.

Key Requirements

  • •10+ years of analog/custom layout design experience in advanced CMOS technology nodes (Planar, FinFET).
  • •5+ years of experience managing layout engineering teams.
  • •Proven ability to lead layout development processes with strong quality oversight.
  • •Bachelor’s or Master’s degree (or equivalent experience) in Electronics, VLSI Engineering, or a related field.
  • •Expertise with Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS, plus hands-on experience with critical IP blocks.
Experience:10+ years
Education:
Skills:CommunicationStakeholder managementMentoringTeam leadershipQuality oversight
Tech Stack:Cadence VLECadence VXLMentor Graphics CalibreLVSDRCAntenna checksPythonSKILLTcl

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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