Custom Layout Design Engineer

AMD
Markham
Workplace: OnsiteTemporaryCAD 75,600 - 129,600 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Collaboration","Issue resolution","Problem-solving"]

Design and implement custom IC layouts for digital and analog circuits based on schematics, using Cadence Virtuoso and advanced semiconductor process technologies. Create and assemble transistor-level cells into macros, develop black-box and abstract models, and contribute to tape-out collateral. Run hierarchical physical verification (DRC, LVS, ERC, EM/IR, latch-up/ESD), drive issue resolution with circuit designers, and explore AI-assisted workflows to improve layout productivity and quality.

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FursaFursa
AMD
AMD
1 day ago

Custom Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Design and implement custom IC layouts for digital and analog circuits based on schematics, using Cadence Virtuoso and advanced semiconductor process technologies. Create and assemble transistor-level cells into macros, develop black-box and abstract models, and contribute to tape-out collateral. Run hierarchical physical verification (DRC, LVS, ERC, EM/IR, latch-up/ESD), drive issue resolution with circuit designers, and explore AI-assisted workflows to improve layout productivity and quality.
Location: Markham
Workplace: Onsite
Employment Type: Temporary
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Create high-quality, manufacturable custom IC layouts for digital and analog building blocks at the transistor level using Cadence Virtuoso.
  • •Perform floorplanning, routing, and assembly of lower-level cells into macros and contribute to top-level integration.
  • •Build black-box and abstract models for other teams and produce tape-out collateral for custom blocks.
  • •Run hierarchical verification at the cell and macro levels (DRC, LVS, ERC, EM/IR, latch-up/ESD) and drive issue resolution with circuit designers.
  • •Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

Pay and Benefits

Salary: CAD 75,600 - 129,600 annually

Key Requirements

  • •Create high-quality, manufacturable transistor-level layouts for digital and analog building blocks and assemble cells into macros.
  • •Demonstrated understanding of CMOS device and circuit theory and analog/digital layout best practices.
  • •Experience with industry-standard layout tools such as Cadence Virtuoso and Calibre.
  • •Experience with physical verification methodologies including LVS, DRC, EM/IR, and ERC (plus latch-up/ESD).
  • •Bachelor’s or master’s degree in Electrical Engineering, Mechanical Engineering, Electronics, or a related technical field.
Experience:SemiconductorsCustom IC layout
Education:Bachelor's in Electrical Engineering, Mechanical Engineering, Electronics, or a related technical field
Skills:CollaborationIssue resolutionProblem-solving
Tech Stack:Cadence VirtuosoCalibreDRCLVSEM/IRERCLatch-upESDFloorplanningRoutingPerlTCLSVRF/TVFSKILL

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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