Design Verification Engineer (Silicon Engineering)

Develop and execute digital ASIC verification across block and system levels for next-generation chips supporting Starlink’s space and ground infrastructure. Own test planning, testbench infrastructure (UVM and non-UVM), regressions, and coverage closure, while writing and reviewing test plans and harnesses. Automate test generation using Python and MATLAB, contribute to pre-silicon verification and chip bring-up, and help validate designs post-silicon.