Silicon Packaging Design Engineer

Intel
Phoenix
Workplace: OnsiteFull timeUSD 105,650 - 149,150 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Problem-solving","Proactive","Communication","Interpersonal","Cross-functional collaboration","Time management","Deadline management","Documentation"]

Drive end-to-end silicon substrate/package design, from concept through tape-out, optimizing for performance, cost, and manufacturability. Own physical layout and routing, run substrate fit/routing studies, define and apply substrate design rules, and resolve design rule check issues. Collaborate with silicon and hardware teams to refine pinout and silicon-package-board interactions, while maintaining documentation through the product lifecycle system of record.

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FursaFursa
Intel
Intel
4 days ago

Silicon Packaging Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Drive end-to-end silicon substrate/package design, from concept through tape-out, optimizing for performance, cost, and manufacturability. Own physical layout and routing, run substrate fit/routing studies, define and apply substrate design rules, and resolve design rule check issues. Collaborate with silicon and hardware teams to refine pinout and silicon-package-board interactions, while maintaining documentation through the product lifecycle system of record.
Location: Phoenix
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Drive physical layout and routing for package designs to align with silicon, package, and board performance requirements.
  • •Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
  • •Define and implement substrate design rules, and conduct internal/external reviews to meet quality standards.
  • •Analyze data and resolve Design Rule Checks (DRCs) to optimize manufacturability and performance.
  • •Complete documentation and collateral into the product lifecycle management system of record.

Pay and Benefits

Salary: USD 105,650 - 149,150 annually
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelor’s with 1+ years of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences, or a Master’s with 6 months of experience in a related field.
  • •6+ months of experience with microelectronic package or PCB physical layout design and manufacturing process.
  • •Familiarity with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
  • •Familiarity with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.
  • •Experience and/or familiarity with end-to-end substrate design work from concept through tape-out.
Experience:1+ yearsMicroelectronicsPCB designHardware designSemiconductor packaging
Education:Bachelor's
Skills:Problem-solvingProactiveCommunicationInterpersonalCross-functional collaborationTime managementDeadline managementDocumentation
Tech Stack:Siemens XpeditionCadence Allegro Package DesignAutoCADSolidWorksPowerDCHyperLynxQ3DHFSSPackage Layout Automation (PLA)FIELDPythonVBC

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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