Senior STA Signoff Methodology Engineer

NVIDIA
Santa Clara, Austin
Workplace: OnsiteFull timeUSD 168,000 - 310,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 8+ yearsEducation: mastersSkills: ["Communication","Collaborative working style","Data analysis","Modeling"]

Drive timing sign-off strategy for NVIDIA’s next-generation GPUs, CPUs, LPUs, and SoCs by modeling advanced effects and optimizing performance, yield, and reliability. Build and refine STA/PNR flows and recommendations across aging, thermal, IR drop, electromigration, and other physical-node challenges. Collaborate with design and timing teams to deploy timing-signoff methodologies, using large-scale SPICE/experimentation and deep data analysis with Python and JMP.

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FursaFursa
NVIDIA
NVIDIA
2 days ago

Senior STA Signoff Methodology Engineer

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Last checked: 11 hours agoStatus: Live

Job Summary

Drive timing sign-off strategy for NVIDIA’s next-generation GPUs, CPUs, LPUs, and SoCs by modeling advanced effects and optimizing performance, yield, and reliability. Build and refine STA/PNR flows and recommendations across aging, thermal, IR drop, electromigration, and other physical-node challenges. Collaborate with design and timing teams to deploy timing-signoff methodologies, using large-scale SPICE/experimentation and deep data analysis with Python and JMP.
Location: Santa Clara, Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Run large-scale SPICE simulations and STA experiments to model chip timing impacts of advanced technologies.
  • •Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electromigration, and other advanced-node physical effects.
  • •Collaborate with technology leads, physical-design, and timing engineers to define and deploy timing-signoff strategies.
  • •Build tools and methodologies to improve design performance, predictability, and silicon reliability beyond standard EDA tools.
  • •Perform extensive data analysis to improve STA-to-silicon correlation across STA, constraints, and timing and power optimization.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually
Equity and Bonus:Equity

Key Requirements

  • •MS in Electrical or Computer Engineering (or equivalent) with 8 years of experience in ASIC design and timing.
  • •Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
  • •Proven foundation in the mathematics and physics underlying electrical design.
  • •Experience with low-power techniques such as multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
  • •Hands-on knowledge of advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm and beyond, plus familiarity with industry-standard ASIC tools like PrimeTime, ICC2, RedHawk, and Tempus.
Experience:8+ yearsASIC designSemiconductorsEDAAdvanced-node hardware
Education:Master's in Electrical Engineering, Computer Engineering
Skills:CommunicationCollaborative working styleData analysisModeling
Tech Stack:SPICESTAPNRPythonJMPPrimeTimeICC2RedHawkTempusTclC++RC extractionDVFSCDCFinFETCMOSActivity-based power analysis

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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