Lead Design Engineer

Cadence Design Systems
Nanjing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Communication","Cross-functional collaboration","Self-starter","Independent ownership","One-team mindset"]

Lead advanced physical IP frontend design for high-performance consumer PHYs, driving architecture from micro-architecture through RTL implementation. You’ll apply expertise in synthesis, constraints, power management, DFT, and low-power techniques, and partner with digital verification, analog, layout, backend design, and lab validation teams to deliver industry-standard IP on schedule. Coordinate pre/post-silicon application support and QA release integration for global customers.

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Cadence Design Systems
Cadence Design Systems
2 hours ago

Lead Design Engineer

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Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Lead advanced physical IP frontend design for high-performance consumer PHYs, driving architecture from micro-architecture through RTL implementation. You’ll apply expertise in synthesis, constraints, power management, DFT, and low-power techniques, and partner with digital verification, analog, layout, backend design, and lab validation teams to deliver industry-standard IP on schedule. Coordinate pre/post-silicon application support and QA release integration for global customers.
Location: Nanjing
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Serve as a key contributor and senior technical engineer in the IP frontend design team for high-performance consumer PHYs (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA).
  • •Drive design architecture to micro-architecture and RTL implementation, refining features and requirements throughout the design process.
  • •Apply understanding of synthesis, constraint generation, power management, and DFT.
  • •Collaborate with digital verification to define coverage points, testing strategy, corner conditions, stimulus creation, and FPGA/Palladium testing.
  • •Partner with project management and multiple engineering groups across Nanjing and global geographies to deliver IP and support pre/post-silicon product engineering and customer releases.

Key Requirements

  • •MS/BS in Electrical/Computer Engineering or a related degree.
  • •5+ years of industry experience with 3+ years in ASIC design for advanced IP and/or ASIC/SOC products.
  • •Deep knowledge of design architecture and RTL design/verification with end-to-end ASIC methodology.
  • •Knowledge of one or more serial standards (e.g., USB, DisplayPort/DP, PCIe, Ethernet).
  • •Strong cross-functional communication in both English and Mandarin, with self-starter and ability to manage multiple priorities.
Experience:5+ years
Education:Master's in Electrical/Computer Engineering
Skills:CommunicationCross-functional collaborationSelf-starterIndependent ownershipOne-team mindset
Languages:EnglishMandarin
Tech Stack:System VerilogPythonC/C++FPGAPalladiumASIC designRTL designSynthesisDFTLow-power designPower islandsState retentionIsolation

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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