Digital Design RTL Engineer

Broadcom
Colorado, United States
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Autonomy","Cross-functional collaboration","Risk mitigation"]

Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), taking designs from initial specification through timing closure and physical design hand-off. Optimize PPA, analyze clock domain crossings (CDC) and reset domain crossings (RDC), and apply low-power design techniques. Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure on-time project milestones.

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FursaFursa
Broadcom
Broadcom
1 month ago

Digital Design RTL Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 days agoStatus: Live
Reposted: similar role first listed 2 months ago

Job Summary

Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), taking designs from initial specification through timing closure and physical design hand-off. Optimize PPA, analyze clock domain crossings (CDC) and reset domain crossings (RDC), and apply low-power design techniques. Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure on-time project milestones.
Location: Colorado, United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Operate with a high degree of autonomy to take designs from initial specification through timing closure and physical design hand-off.
  • •Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones.
  • •Apply high proficiency in SystemVerilog to deliver RTL in advanced process nodes (5nm and below).
  • •Optimize PPA and analyze clock domain crossings (CDC) and reset domain crossings (RDC).
  • •Implement low-power design techniques to support project requirements and schedules.

Pay and Benefits

Perks:Health InsuranceDentalVision401kEsppEmployee AssistancePaid HolidaysPaid LeaveParental Leave

Key Requirements

  • •BSEE required; MSEE or PhD preferred.
  • •Proven track record delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below).
  • •Deep understanding of RTL design, PPA optimization, and clock domain crossing (CDC) analysis.
  • •Experience with reset domain crossing (RDC) and low-power design techniques.
  • •8+ years of industry experience, preferably with SoC integration and high-speed SerDes and/or LPDDR/DDR and/or HBM protocols.
Experience:8+ yearsSoC integrationHigh-speed SerDesLPDDR/DDRHBMAdvanced process nodesLow-power design
Education:Bachelor's
Skills:AutonomyCross-functional collaborationRisk mitigation
Tech Stack:SystemVerilogRTL designPPA optimizationCDCRDCLow-power designSoC integrationSerDesLPDDRDDRHBM

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn