Digital Design RTL Engineer

Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), taking designs from initial specification through timing closure and physical design hand-off. Optimize PPA, analyze clock domain crossings (CDC) and reset domain crossings (RDC), and apply low-power design techniques. Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure on-time project milestones.