ASIC Design Verification Engineer

Broadcom
Irvine
Workplace: OnsiteFull timeUSD 129,400 - 207,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Teamwork","Communication","Problem-solving","Leadership","Attention to detail"]

Contribute to the verification of next‑gen Broadcom ASICs for Ethernet systems in the cloud. Work with SystemVerilog and UVM to verify high‑throughput designs, driving coverage closure across a globally distributed team. Opportunity to lead aspects of Design Verification and collaborate with design/architecture teams on new devices.

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FursaFursa
Broadcom
Broadcom
3 months ago

ASIC Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 28 days agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Contribute to the verification of next‑gen Broadcom ASICs for Ethernet systems in the cloud. Work with SystemVerilog and UVM to verify high‑throughput designs, driving coverage closure across a globally distributed team. Opportunity to lead aspects of Design Verification and collaborate with design/architecture teams on new devices.
Location: Irvine
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Verify new ASIC designs using constrained random verification methodologies with a focus on achieving coverage closure
  • •Develop, maintain and enhance SystemVerilog/UVM based testbenches and environments
  • •Collaborate with worldwide design/architecture teams to verify high‑throughput Ethernet solutions and AI/ML workflow acceleration
  • •Contribute to technical leadership and drive verification progress across generations
  • •Participate in design verification strategy and methodology improvement

Pay and Benefits

Salary: USD 129,400 - 207,000 annually
Equity and Bonus:Equity
Perks:MedicalDentalVision401kEsppEapPaid Leave

Key Requirements

  • •Constrained random verification methodologies with experience driving completion via coverage closure
  • •Strong skills with SystemVerilog and UVM; experience with object-oriented programming (OOP)
  • •Experience with SV testbenches, UVM, VCS or Incisive, and scripting (Python, Perl)
  • •Bachelor's degree with 12+ years of related experience, or Master's with 10+ years, or PhD with 3+ years
  • •Ability to work with worldwide design and architecture teams to develop leading edge products
Experience:12+ yearsSemiconductorASICEthernetAICloud
Education:Bachelor's
Skills:TeamworkCommunicationProblem-solvingLeadershipAttention to detail
Languages:English
Tech Stack:SystemVerilogUVMVCSIncisivePythonPerl

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn