Senior DRAM RTL design engineer
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3-6 yearsEducation: mastersSkills: ["Collaboration","Problem-solving","Communication","Technical mentorship"]Design digital IP blocks for DRAM from microarchitecture through RTL creation, integration, and support of physical hardware development. Define module interfaces and system-level architecture, and use AI-based tools and agentic workflows to accelerate RTL design optimization, testbench generation, and debug efficiency. Drive full-chip integration and verification across CDC, Lint, synthesis, STA, power analysis, and collaborate across CAD/EDA, software, architecture, and physical design teams.
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