Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: mastersSkills: ["Leadership","Mentoring","Teamwork","Code review culture","Problem solving"]

Lead ASIC design verification for Cisco SiliconOne, driving end-to-end verification from specification through tape-out and lab validation. Build and enhance SystemVerilog/UVM testbenches, define verification methodologies, and own DV architecture decisions. Collaborate with design, architecture, emulation, software, and post-silicon validation teams to verify ASICs in simulation and emulation, including gate-level simulation and SDF back-annotation. Mentor engineers and ensure high-quality, high-performance delivery for high-volume products.

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FursaFursa
Cisco
Cisco
1 day ago

Leader/Manager, ASIC Design Verification Engineering || Verilog, UVM, TestBench, Technical Leadership, Hardware Emulation, SOC || Exp - 15 + years

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Last checked: 9 hours agoStatus: Live

Job Summary

Lead ASIC design verification for Cisco SiliconOne, driving end-to-end verification from specification through tape-out and lab validation. Build and enhance SystemVerilog/UVM testbenches, define verification methodologies, and own DV architecture decisions. Collaborate with design, architecture, emulation, software, and post-silicon validation teams to verify ASICs in simulation and emulation, including gate-level simulation and SDF back-annotation. Mentor engineers and ensure high-quality, high-performance delivery for high-volume products.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead and mentor ASIC design verification teams delivering high-performance, high-quality ASICs for Cisco product platforms.
  • •Define and verify ASICs and ASIC subsystems, ensuring alignment with stringent quality requirements for deployment.
  • •Collaborate with design and hardware teams to verify ASICs in simulation, emulation, and during bring-up.
  • •Build and enhance UVM/SystemVerilog testbenches, and define or improve DV methodologies for reuse and efficiency.
  • •Own end-to-end verification activities including test plan generation/review/execution, gate-level simulation with SDF back-annotation, coverage run/merging, and participation across RTL verification, emulation, and post-silicon validation.

Key Requirements

  • •15+ years of hands-on experience in large-scale, high-performance ASIC design verification.
  • •BS/MS plus prior experience leading a design team for at least 5+ years.
  • •Hands-on SystemVerilog and UVM methodology experience, including developing UVM-based infrastructure from scratch on multiple projects.
  • •Working knowledge of C/C++ programming and debugging for verification and hardware/software bring-up.
  • •Proficiency with coverage-based simulation (code/functional coverage), coverage data analysis/merging, and test planning for ASIC verification.
Experience:15+ yearsASICSoC
Education:Master's
Skills:LeadershipMentoringTeamworkCode review cultureProblem solving
Tech Stack:SystemVerilogVerilogUVMC++CUVM testbenchesTestbenchHardware emulationSoCASICC/C++ programmingScriptingMakefilesEVEVeloceSDF back annotationGate-level simulationRTL verificationEmulation infrastructureCoverage collection

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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