Principal Product Engineer

Cadence Design Systems
Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 10+ yearsEducation: mastersSkills: ["Debugging","Problem-solving","Communication","Presentation","Issue management","Customer focus"]

Serve as the primary technical interface for strategic customer engagements in the DDR IP division, supporting deployment of DDR PHY IP solutions in post-silicon environments. Own debugging and bringup for customer silicon issues across systems and ATE, using lab instrumentation (oscilloscopes, BERTs, protocol exercisers) and SI/PI analysis. Manage customer support cases in SFDC using tools like Sherlock and JIRA, with an emphasis on AI-augmented productivity and actionable insights.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
7 hours ago

Principal Product Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 3 years ago

Job Summary

Serve as the primary technical interface for strategic customer engagements in the DDR IP division, supporting deployment of DDR PHY IP solutions in post-silicon environments. Own debugging and bringup for customer silicon issues across systems and ATE, using lab instrumentation (oscilloscopes, BERTs, protocol exercisers) and SI/PI analysis. Manage customer support cases in SFDC using tools like Sherlock and JIRA, with an emphasis on AI-augmented productivity and actionable insights.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Serve as the primary technical liaison for deploying DDR PHY IP solutions during strategic customer engagements.
  • •Debug customer silicon issues for both systems and ATE in a post-silicon environment.
  • •Use lab equipment (oscilloscopes, BERTs, protocol exercisers, analyzers) to reproduce and analyze customer failures.
  • •Apply SI/PI requirements and assist in diagnosing related hardware issues for the IP.
  • •Own and coordinate customer support cases in SFDC using tools such as Sherlock and JIRA, including about 10% travel for onsite bringup and debug.
Travel: Low travel

Key Requirements

  • •M.S. in Electrical/Computer Engineering (or similar) with 10+ years of experience, or a PhD with 5+ years of relevant experience.
  • •Experience working with Memory PHY, Memory Controller, and DRAM.
  • •Experience with advanced mixed-signal verification and system simulation tools.
  • •Strong background in supporting post-silicon bringup and debugging, including familiarity with advanced technology nodes (7nm and below).
  • •Hands-on lab experience to reproduce customer failures, plus strong presentation and communication skills.
Experience:10+ yearsSemiconductorsHardwarePost-siliconMemoryAI-augmented development
Education:Master's in Electrical/Computer Engineering
Skills:DebuggingProblem-solvingCommunicationPresentationIssue managementCustomer focus
Tech Stack:DDRLPDDRGDDRDDR PHY IPPost-siliconATEOscilloscopesBERTsProtocol exercisersAnalyzersSignal integrity (SI)Power integrity (PI)Mixed signal verificationSystem simulationSFDCSherlockJIRAAI-powered tools and assistants7nm

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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