Sr. Principal Design Engineer
Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","Perl","Unix shell","Cadence Xcelium","Indago","AXI","AHB","APB"]Lead design verification for interconnect IP and Tensilica processor subsystems at Cadence. Develop and execute verification plans, build UVM-based environments, and drive coverage closure in collaboration with DV, architecture, design, and firmware teams. Requires 10+ years of design verification, strong SystemVerilog/UVM, and expertise in AMBA AXI/AHB/APB protocols.
